Efficient memory simulation in SimICS

摘要: We describe novel techniques used for efficient simulation of memory in SimICS; an instruction level simulator developed at SICS. The design has focused on efficiently supporting the multiprocessors, analyzing complex hierarchies and running large binaries with a mixture system user code. A software caching mechanism (the Simulator Translation Cache, STC) improves performance interpreted operations by reducing number calls to Major data structures are allocated lazily reduce size process. well defined internal interface generic simplifies extensions. Leveraging flexible interpreter based threaded code allows runtime selection statistics gathering, profiling, cache low overhead. result is scheme that supports range features use computer architecture research, program debugging. >