Margins and yield in single flux quantum logic
作者： C.A. Hamilton , K.C. Gilbert
DOI: 10.1109/77.107400
关键词:
摘要: Simulations are used to optimize the design of simple rapid single flux quantum (RSFQ) logic gates and determine their margins. Optimizations based on maximizing smallest (critical) margin result in critical margins range 19-50%. A Monte Carlo approach is illustrate relationship between process yield. Based gate simulations, results show that 1 sigma parameter spreads less than about +or-5% will be required make medium- or large-scale integrated RSFQ circuits. single-bit full adder using five a local self-timing network simulated with discrete components. The 2000-A/cm/sup 2/ junctions specific capacitance 0.04 pF/ mu /sup had delay 87 ps worst-case +or-19%. small reduction which not present individual simulations from loading. >
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