High and low speed output buffer design with reduced switching noise for USB applications

摘要: Novel frequency doubler circuits and dividers for clock signal generation are presented. In combination with two edge detectors duty cycle control buffers a low cost circuit is achieved as compared to Phase-Locked Loop (PLL) design. An input an unpredictable inputted rising (or falling) detector. The detector converts the positive negative) transitions one shot pulse train whose same that of clock. However, has its far less than 50%. By first 50% buffer output waveform resulted symmetrical. first-stage then detected by falling detector, so twice incoming signal. Finally, second signals adjusted in second-stage buffer, restore cycle. Therefore, times multiplication Furthermore, novel design approach using also demonstrated. Simulation results both division confirm validity proposed approach.