Digital sequence detector

摘要: A system for detecting the successful detection of a known serial data sequence L bits. The comprises clock pulse generating means train pulses at rate f c , shift register having N stages each with an output terminal serially receiving said fc and supplying contents stage to thereof, memory least M terminals, N+M input X locations accessable by predetermined address supplied terminals supply location terminals. Further provided is latch responsive signals on such back time interval Δ after entering bit into means, where Δ<1/f . are selected advance through first binary patterns when addressed second M+N addresses; addresses formed sequences coinciding contained in continue outputting until completely received.