Bus interconnect system

摘要: An interconnect system (SI) adapted for acting as a data path transferring data fields on a bus between a plurality of initiators (I1, I2) and targets (T1, T2) operates in such way that each field is transferred during respective cycle corresponding clock signal. The is configured (10, 11) a way the said are divided into first and second part. Similarly, clock signal first The first part are transferred, respectively, the second clock Data fields having size 128 bits, example, can thus be transferred 64-bit structure without any negative effect performance the necessity increasing frequency; this facilitates integration chip.