作者: Tze-Yun Sung
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摘要: Two-dimensional discrete cosine transform (DCT) and inverse (IDCT) have been widely used in many image processing systems. In this paper, efficient architectures with parallel pipelined structures are proposed to implement 8 × DCT IDCT processors. which, only one bank of SRAM (64 words) coefficient ROM (6 is utilized for saving the memory space. The kernel arithmetic unit, i.e. multiplier, which demanding implementation processors, has replaced by simple adders shifters based on CORDIC algorithm. 2-D processors not simplify hardware but also reduce power consumption high performances.