Clock generation circuit and bus system

摘要: PURPOSE:To reduce the clock skew of a two phase clock. CONSTITUTION:One output adjustment mechanism reaches normal load point through an equal delay circuit 7 and distribution 9. A at is inputted to comparator 3 it compared with reference phase. Then, comparison signal outputted. variable 5 controlled so that matched in accordance signal. The other 1 becomes by means 8 generation system, 10. delays except for are adjusted between path from point. almost matches original oscillation. reduces against