作者: Taehee Cho , Yeong-Taek Lee , Eun-Cheol Kim , Jin-Wook Lee , Sunmi Choi
DOI: 10.1109/4.962291
关键词:
摘要: A 116.7-mm/sup 2/ NAND flash memory having two modes, 1-Gb multilevel program cell (MLC) and high-performance 512-Mb single-level (SLC) is fabricated with a 0.15-/spl mu/m CMOS technology. Utilizing simultaneous operation of four independent banks, the device achieves 1.6 6.9 MB/s throughputs for MLC SLC respectively. The two-step bitline setup scheme suppresses peak current below 60 mA. wordline ramping technique avoids disturbance. mode uses 0.5-V incremental step pulse self-boosting inhibit to achieve high performance, 0.15-V local tightly control threshold voltage V/sub th/ distributions. With small pitches 0.3-/spl 0.36-/spl mu/m, respectively, t/h shift due floating gate coupling about 0.2 V. read margins between adjacent states are optimized resulting in nonuniform distribution mode.