作者: John F. Zumkehr , Amir A. Abouelnaga
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摘要: Systems and methods for transient error recovery in pipelined reduced instruction set computer (RISC) processors prevent state changes based on the execution of an until is validated. If a fault occurs causing to appear execution, retrieved using fetch address associated with that stored pipeline history cache. The RISC processor then restarted instruction. validation may take place stage, though high clock frequencies include separate validate stage so there adequate time without having decrease frequency.