Arrangement for improving defect scanner sensitivity and scanning defects on die of a semiconductor wafer

摘要: Defect scanner sensitivity and accuracy are improved for light scattering defect scanners pattern matching by calibrating the to each die on a wafer using preset marks corresponding die. The have predetermined size based of position relative circuit Alignment specific provides improvement in coordinate over alignment with respect an entire wafer. A layout mapping filtering system collects scan data determines interaction between detected defects layout. automatic identification real time killer that cause failure completed integrated circuit, classifies analyzes identify potential within specified classes defective accurate yield estimation determine whether produced should be scrapped, also accumulated studies including quality control redesign.