An algorithmic and novel design of a leading zero detector circuit: comparison with logic synthesis

摘要: A novel way of implementing the leading zero detector (LZD) circuit is presented. The implementation based on an algorithmic approach resulting in a modular and scalable for any number bits. We designed 32 64 bit CMOS ECL technology. version was using both: logic synthesis approach. compared with results obtained modern tools same 0.6 /spl mu/m showed advantage to produced by synthesis. LZD simulated perform under 200 ps nominal speed. >