Reducing the complexity of finite state machine test generation using combinatorial designs

摘要: A design verification system generates a small set of test cases, from finite state machine model the application under test. The is reduced by creating efficient samples inputs to which are prepared combinatorial input parameter selection. cases generated traversal machine, and tests interacting combinations parameters in an way. technique integrated into generator based on machine. Using extended language, partial rulesets employed instruct automatically employ selection during generation. Another for case generation disclosed, uses algorithms guarantee coverage aspect interaction between stimuli at different stages or transitions case.