High-Speed Modular Multiplier for Lattice-Based Cryptosystems

摘要: Thanks to the inherent post-quantum resistant properties, lattice-based cryptography has gained increasing attention in various cryptographic applications recently. To facilitate practical deployment, efficient hardware architectures are demanded accelerate operations and reduce computational resources, especially for polynomial multiplication, which is bottleneck of cryptosystems. In this brief, we present a novel high-speed modular multiplier architecture multiplication. The proposed employs divide conquer strategy exploits special modulus increase parallelism speed up calculation, while enabling wider across experimental results show that our design achieves around 27% 39% reduction on area consumption delay, respectively, compared prior works.