An On-chip Calibration Technique for Reducing Supply Voltage Sensitivity in Ring Oscillators
作者： Ting Wu , Kartikeya Mayaram , Un-Ku Moon
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摘要: A technique for reducing the supply voltage sensitivity of a ring oscillator using on-chip calibration is described. 1-V 0.13-mum CMOS PLL demonstrates robust performance against VCO noise over operating frequencies 0.5 to 2 GHz. In presence 10-mV 1-MHz noise, measured rms jitter proposed with 3.95 ps at 1.4-GHz frequency, while conventional design measures 8.22 jitter. For 10-MHz improved from 16.8 3.97 ps. The total power consumption 9.6 mW 1.4 GHz, and combined core die area circuitry 0.064 mm2
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sci-hub.se 参考文章(11)
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