Providing variable interpretation of usefulness indicators for memory tables in processor-based systems
作者： Krishna Anil , Kothinti Naresh Vignyan Reddy , Wright Gregory Michael , Rotenberg Eric , Yi Yongseok
DOI:
关键词:
摘要: Providing variable interpretation of usefulness indicators for memory tables in processor-based systems is disclosed. In one aspect, a system comprises table providing multiple entries, each including indicator. A controller the global polarity indicator representing how entry interpreted and updated by controller. If set, interprets value as directly corresponding to entry. Conversely, if not reversed such that inversely this manner, updating can be varied using
lens.org 参考文章(12)
Tomas G. Akenine-Moller, Jim K. Nilsson, Color buffer caching ,(2012)
Alper Buyuktosunoglu, Jude A. Rivers, Hillery C. Hunter, Vijayalakshmi Srinivasan, Xiaochen Guo, Pradip Bose, Processor with memory-embedded pipeline for table-driven computation ,(2013)
Yasahiro Endo, Konstantinos Roussos, Dynamic streaming buffer cache algorithm selection ,(2002)
Timothy J. Millet, James B. Keller, James Wang, Zongjian Chen, Cache implementing multiple replacement policies ,(2009)
Michael Henry Kass, Memory System Cache Eviction Policies ,(2013)
Michael Wintergerst, Petio G. Petev, Least recently used eviction implementation ,(2004)
Sanjay Vishin, Ryan C. Kinter, Avoiding Livelock Using A Cache Manager in Multiple Core Processors ,(2007)
Sharma Prabal, ELECTRONIC SYSTEM WITH LOW CONFIDENCE PREDICTION AND METHOD OF OPERATION THEREOF ,(2015)
Andreas Gotterba, Gil I. Winograd, Esin Terzioglu, Multi-port sram with six-transistor memory cells ,(2008)
Toshio Matsumoto, Priority-based memory management method and apparatus ,(1994)