Linear jitter attenuator

摘要: A jitter attenuation circuit includes a FIFO data register (10) which is operable to receive that synchronized with Write clock output therefrom Read clock. The written the from location determined by pointer (12). read out (14) clocked phase lock loop (24). (24) has detector (26) accrue error over intervals of 2π radians such virtually never loses as result on contained therein digitally controlled linear oscillator (28) wherein provides quantized incrementally step up or down in frequency track while attenuating thereon.