An ANSI standard ISDN transceiver chip set

摘要: The authors describe a two-chip ISDN U-interface transceiver based on the American National Standards Institute (ANSI) 2B1Q line code. two chips are analog front-end (AFE) which performs interfacing and data conversion functions digital subscriber loop (DSL) processor algorithm-specific signal processing (ASSP) in receive path addition, control, maintenance, access (CMA). ASSP decimation of sigma-delta modulator output from AFE, linear nonlinear echo cancellation, automatic gain interpolation, decision feedback equalization, timing recovery. CMA provides to interface such as wire polarity check, rate conversion, framing, cyclic redundancy code generation scrambling descrambling, activation-deactivation, start-up control. Successful operation prototype chip sets has been demonstrated laboratory environment for 26-gauge cable lengths up 18000 ft. >