摘要: This is a survey on the algorithms which are part ofa program for flat placement of large-scale VLSI processorchips. The basis quadratic optimization approachcombined with new quadrisection algorithm.In contrast to most previous methods,no min-cut objective used at all. Based aquadratic placement, completely algorithm findsa four-way partitioning meeting capacity constraintsand minimizing total movement.
core.ac.uk
acm.org
sci-hub.se 参考文章(6)
J.M. Kleinhans, G. Sigl, F.M. Johannes, K.J. Antreich, GORDIAN: VLSI placement by quadratic programming and slicing optimization IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. ,vol. 10, pp. 356- 365 ,(1991) , 10.1109/43.67789
J. Schietke, U. Fassnacht, Timing analysis and optimization of a high-performance CMOS processor chipset design, automation, and test in europe. pp. 325- 330 ,(1998) , 10.5555/368058.368165
Ren-Song Tsay, E.S. Kuh, Chi-Ping Hsu, PROUD: a sea-of-gates placement algorithm IEEE Design & Test of Computers. ,vol. 5, pp. 44- 56 ,(1988) , 10.1109/54.9271
J. Koehl, T. Pflueger, T. Ludwig, B. Kick, U. Baur, A flat, timing-driven design system for a high-performance CMOS processor chipset design, automation, and test in europe. pp. 312- 320 ,(1998) , 10.5555/368058.368161
Yo Taniguchi, Keikichi Tamaru, Branch-and-bound placement for building block layout design automation conference. pp. 433- 439 ,(1991) , 10.1145/127601.127708
James B. Orlin, A Faster Strongly Polynomial Minimum Cost Flow Algorithm Operations Research. ,vol. 41, pp. 338- 350 ,(1993) , 10.1287/OPRE.41.2.338