Digital filter for filtering and decimating delta sigma modulator output signals

摘要: An oversampled interpolative delta sigma analog-to-digital converter including a modulator is provided with cascade of bit-slice elements at the output to form filter/decimator. Each element includes filter circuit that filters bit-rate signal in accordance an arbitrary impulse response input provide characteristic can be controllably varied without modifying hardware. In each element, adder and delay decimate produced by digital clock cycle rate equal Nyquist rate. The filter/decimator also provides encoding 2's complement format.