Protocol for memory power-mode control
作者： Kishore Ven Kasamsetty , Frederick A. Ware , Lawrence Lai , Akash Bansal , Wayne F. Ellis
DOI:
关键词:
摘要: In one embodiment, a memory device includes core and input receivers to receive commands data. The also register store value that indicates whether subset of the are powered down in response control signal. A controller transmits data device. indicate addition, self-fresh command, defers entry into self-refresh operation until receipt signal is received after receiving command.
lens.org 参考文章(106)
Jeng-Feng Lan, Hon-Shing Lau, Jr-Houng Lu, Power down system for regulated internal voltage supply in DRAM ,(2000)
Neville K. S. Lee, John S. Berg, Flying head with adjustable actuator load ,(1997)
Thierry Gourbilleau, Sebastien Jouin, Estelle Fazilleau, Patrice Menard, Clock generator circuit with automatic sleep mode ,(2013)
Chang-eun Choi, Nonvolatile memory device having operation mode change function and operation mode change method ,(2011)
Choung-Ki Song, Semiconductor memory device including clock control circuit and method for operating the same ,(2010)
Hiroki Fujisawa, Latency counter, semiconductor memory device including the same, and data processing system ,(2009)
Ho-beom Park, Jin-Kyu Park, Jin-Won Jung, Image forming apparatus, microcontroller, and methods for controlling image forming apparatus and microcontroller ,(2012)
Timothy B. Cowles, Hua Zheng, Jeffrey P. Wright, Method and apparatus for controlling the operation of an integrated circuit responsive to out-of-synchronism control signals ,(2000)
Frederick A. Ware, Brent Haukness, Protocol for refresh between a memory controller and a memory device ,(2010)
Brent Keeth, Jeffrey P. Wright, Jeffery W. Janzen, James S. Cullum, System and method for decoding commands based on command signals and operating state ,(2005)