Hardware Acceleration of Gate Array Layout

摘要: In this paper we describe the hardware and software of a system which have implemented to accelerate physical design gate arrays. contrast nearly all other reported approaches, our approach acceleration is augment single-user host workstation with general-purpose microprogrammable slave processor having large private memory. One or more such slaves can be attached. We placement improvement on system, achieving 20 x speedup vs. high-level implementation. give performance results, are comparable those elsewhere for mainframe implementations.