An efficient routing algorithm for irregular mesh NoCs

作者: Parisa Mahdavinia , Hamid Sarbazi-Azad

DOI: 10.1109/ISCAS.2010.5537936

关键词:

摘要: Many researchers favor the mesh topology as underlying of communication infrastructure modern SoCs because its regularity and layout efficiency. However, variability in size shape modules used systems-on-chip has resulted use irregular meshes for practical NoCs. In this paper, we propose a deadlock free routing algorithm Experimental results confirm that proposed exhibits better performance terms message latency power consumption compared to other known algorithms

参考文章(20)
Christopher J. Glass, Lionel M. Ni, Maximally Fully Adaptive Routing in 2D Meshes. international conference on parallel processing. pp. 101- 104 ,(1992)
Christopher J. Glass, Lionel M. Ni, The turn model for adaptive routing Journal of the ACM. ,vol. 41, pp. 874- 902 ,(1994) , 10.1145/185675.185682
Younes M. Boura, Chita R. Das, A Class of Partially Adaptive Routing Algorithms for n_dimensional Meshes international conference on parallel processing. ,vol. 3, pp. 175- 183 ,(1993) , 10.1109/ICPP.1993.16
JIE WU, LI SHENG, DEADLOCK-FREE ROUTING IN IRREGULAR NETWORKS USING PREFIX ROUTING Parallel Processing Letters. ,vol. 13, pp. 705- 720 ,(2003) , 10.1142/S0129626403001616
J. Duato, A new theory of deadlock-free adaptive routing in wormhole networks IEEE Transactions on Parallel and Distributed Systems. ,vol. 4, pp. 1320- 1331 ,(1993) , 10.1109/71.250114
M. Koibuchi, A. Funahashi, A. Jouraku, H. Amano, L-turn routing: an adaptive routing in irregular networks international conference on parallel processing. pp. 383- 392 ,(2001) , 10.1109/ICPP.2001.952084
Andrew A. Chien, Jae H. Kim, Planar-adaptive routing: low-cost adaptive networks for multiprocessors Journal of the ACM. ,vol. 42, pp. 91- 123 ,(1995) , 10.1145/200836.200856
A. Nayebi, S. Meraji, A. Shamaei, H. Sarbazi-Azad, XMulator: A Listener-Based Integrated Simulation Platform for Interconnection Networks asia international conference on modelling and simulation. pp. 128- 132 ,(2007) , 10.1109/AMS.2007.112
M. Glesner, M. K. F. Schafer, H. Zimmer, T. Hollstein, Deadlock-free routing and component placement for irregular mesh-based networks-on-chip international conference on computer aided design. pp. 238- 245 ,(2005) , 10.5555/1129601.1129636
S. Kumar, A. Jantsch, J.-P. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja, A. Hemani, A network on chip architecture and design methodology ieee computer society annual symposium on vlsi. pp. 117- 124 ,(2002) , 10.1109/ISVLSI.2002.1016885