Modular Hardware Architecture for Somewhat Homomorphic Function Evaluation

摘要: We present a hardware architecture for all building blocks required in polynomial ring based fully homomorphic schemes and use it to instantiate the somewhat encryption scheme YASHE. Our implementation is first FPGA that designed evaluating functions on homomorphically encrypted data (up certain multiplicative depth) we illustrate this capability by SIMON-64/128 block cipher domain. provides fast operations unit using CRT NTT multiplication combined with an optimized memory access scheme; Barrett like reduction method; efficient divide round of ciphertexts unit. These are integrated instruction-set coprocessor execute YASHE, which can be controlled computer arbitrary depth 44 128-bit security level). was compiled single Virtex-7 XC7V1140T FPGA, where consumes 23 % registers, 50 LUTs, 53 DSP slices, 38 BlockRAM memory. The evaluates approximately 157.7 s (at 143 MHz) processes 2048 at once giving relative time only 77 ms per block. This 26.6 times faster than leading software 4-core Intel Core-i7 processor running 3.4 GHz.