A Scalable and Modular Architecture for High-Performance Packet Classification

摘要: Packet classification is widely used as a core function for various applications in network infrastructure. With increasing demands throughput, performing wire-speed packet has become challenging. Also the performance of today's solutions depends on characteristics rulesets. In this work, we propose novel modular Bit-Vector (BV) based architecture to perform high-speed Field Programmable Gate Array (FPGA). We introduce an algorithm named StrideBV and modularize BV achieve better scalability than traditional methods. Further, incorporate range search our eliminate ruleset expansion caused by range-to-prefix conversion. The post place-and-route results implementation state-of-the-art FPGA show that proposed able operate at 100+ Gbps minimum size packets while supporting large rulesets up 28 K rules using only on-chip memory resources. Our solution ruleset-feature independent , i.e. above can be guaranteed any regardless composition ruleset.