High-speed digital multiplier architecture

摘要: A high-speed digital multiplier architecture is implemented in a bipolar very large scale integrated circuit technology. Operand input and product output latches are independently enabled by inverted clock signals. The can be operated unclocked, separately clocked single or master-slave modes of operation. to concatenate, rather than multiply, the operands thereby load directly from inputs output. selectable format adjust performs one bit left shift on product. low order zero inserted shifted product, an overflow flag set case -1.0×-1.0=1.0, rounding correct for both adjusted unadjusted products. provided which rounded unrounded negative provides unambiguous indicator sign signed mixed mode