A Compact Fading Channel Simulator Using Timing-Driven Resource Sharing
作者： A. Alimohammad , B.F. Cockburn , S.F. Fard , C. Schlegel
DOI: 10.1109/ASAP.2007.4429973
关键词:
摘要: This paper presents a computationally-efficient design and implementation technique for fading channel simulators. Our fixed-point of Rayleigh simulator on field-programmable gate array (FPGA) utilizes only 4% the configurable slices, 19% dedicated multipliers, 2% on-chip memory blocks, while generating 12.5 million statistically accurate variates per second. The designed emulator can be parameterized to simulate wide variety different characteristics over bandwidths up MHz. compact also instantiated multiple times assess performance communication systems multiple-input multiple-output (MIMO) channels.
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