Pipelined data processing including program counter recycling
作者： Douglas Deao , Gary L. Swoboda , Mark R. Hammes , Nick Ing-Simmons , Keith Balmer
DOI:
关键词:
摘要: In a pipeline data processor (11), an address (39, 41) id provided to hold the addresses of instructions presently in instruction (23, 25). The facilitates tracing only executed instructions, and permits stopping during branch delay slot without losing information.
lens.org 参考文章(23)
Gordon H. Matthews, Method and apparatus for assisting in debugging of a digital computer program ,(1974)
Richard Deming Smith, Computer with program tracing facility ,(1970)
Alexander Wolfe, Rodnay Zaks, From chips to systems : an introduction to microcomputers SYBEX. ,(1987)
Norman P. Jouppi, System and method for processor pipeline control by selective signal deassertion ,(1990)
Toyohiko Yoshida, Microprocessor having program counter registers for its coprocessors ,(1990)
John J. Bradley, Ming T. Miu, Program counter stacking method and apparatus for nested subroutines and interrupts ,(1982)
David J. Sager, Simon C. Steely, Register mapping system having a log containing sequential listing of registers that were changed in preceding cycles for precise post-branch recovery ,(1990)
Joseph C. Krauskopf, Microprocessor breakpoint apparatus ,(1988)
Victor Shih-Yuan Lee, Steven Lee Gregor, Directed hardware error identification method and apparatus for error recovery in piplined processing areas of a computer system ,(1989)