An 8 GHz First-Order Frequency Synthesizer for Low-Power On-Chip Clock Generation

摘要: This paper presents a low-power first-order frequency synthesizer architecture suitable for high-speed on-chip clock generation. The proposed design features an combining LC quadrature voltage-controlled oscillator (VCO), two sample-and-holds, phase interpolator, digital coarse-tuning and rotational detection fine-tuning. Similar to multiplying delay-locked loops (MDLLs), this limits jitter accumulation one reference cycle, as during cycle does not contribute the next cycles. Also, instead of using multiplexer switches commonly employed in MDLLs, edge is injected by interpolation support higher frequencies lower jitter. Functionality validated between 8–9.5 GHz, VCO's range operation. First-order dynamic acquisition has been analyzed demonstrated through measurement. output at 8 GHz integrated rms 490 fs, peak-to-peak periodic 2.06 ps total 680 fs. Different components have separate measurements done analysis. spurs are measured be $-$ 64.3 dB below carrier frequency. At system consumes 2.49 mW from 1 V supply.