Non-uniform wordlength delay lines for FIR filters

摘要: When FIR filters are designed floating point arithmetic is generally used. However when implemented on hardware such as ASICs, fixed must be used to minimise cost and power requirements. Research costs has mainly focused the quantization effects of wordlengths for coefficients, multipliers adders filters, but with actual data delays assigned a uniform wordlength essentially not optimised. This paper proposes that delay line can non-uniform minimal increase in noise parallel implementation where there differences magnitudes coefficients. A allows savings terms register wordlengths, signal multiplier wordlengths. Results an design presented which demonstrate using line.