Method and apparatus for interconnecting busses in a multibus computer system
作者： Elbert Bloom , Victoria M. Triolo , David W. Hartwell
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摘要: A bus adapter connecting a high-speed pended (25) to slower speed non-pended (45) includes first module (69) functioning as node of the and second (61) bus. An interconnect (611) extends between two modules. Control signals on generated by comprise status having an indefinite assertion duration, are deasserted only in response control module, which have finite duration. synchronized dual-rank synchronizer controlled phases multiphase clock signal derived from signal.
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