Real time fault tolerant error correction mechanism

摘要: The present invention provides a real-time fault-tolerant hardware error correction device which is typically implemented as data transfer circuit between disc memory and processing unit. It operates in two modes: an encoding system detector on write, decoding corrector read. In its first mode, each block of from the unit encoded with syndrome it transmitted to memory. Two identical linear feedback shift registers (LFSR's) are used for detection purposes. second same LFSR's buffer achieve correction. Data flow alternated block-by-block, one being received by LFSR succeeding other LFSR. At time that channeled particular LFSR, synchronously While incoming block, providing output signals correct previous leaving new arrives.