Consistency and event ordering in the shared regions model
作者： Harjinder S. Sandhu
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摘要: The Shared Regions model introduces abstractions at the programming level that explicitly relate shared data with synchronization primitives guard access to data. In this paper, we discuss consistency and event ordering in model. We show that, using such a model, it is possible relax constraints on of memory operations beyond those any previous models. Additionally, by taking advantage fact events are labeled as readaccess or writeaccess system can significantly improve concurrency allowing processor modifying some execute concurrently processors reading Some implementations exploiting relaxed increased also discussed.
参考文章(14)
Harjinder S. Sandhu, Integrating applications with cache and memory management on a shared-memory multiprocessor conference of the centre for advanced studies on collaborative research. pp. 382- 393 ,(1992)
Michael J. Feeley, Henry M. Levy, Distributed shared memory with versioned objects conference on object oriented programming systems languages and applications. ,vol. 27, pp. 247- 262 ,(1992) , 10.1145/141936.141957
Harjinder S. Sandhu, Benjamin Gamsa, Songnian Zhou, The shared regions approach to software cache coherence on multiprocessors Proceedings of the fourth ACM SIGPLAN symposium on Principles and practice of parallel programming - PPOPP '93. ,vol. 28, pp. 229- 238 ,(1993) , 10.1145/155332.155356
Per Brinch Hansen, None, Concurrent Programming Concepts ACM Computing Surveys. ,vol. 5, pp. 223- 245 ,(1973) , 10.1145/356622.356624
Dennis Shasha, Marc Snir, Efficient and Correct Execution of Parallel Programs That Share Memory ,(2011)
Kourosh Gharachorloo, Sarita V. Adve, Anoop Gupta, John L. Hennessy, Mark D. Hill, Programming for different memory consistency models Journal of Parallel and Distributed Computing. ,vol. 15, pp. 399- 407 ,(1992) , 10.1016/0743-7315(92)90052-O
C. Scheurich, M. Dubois, Correct memory operation of cache-based multiprocessors international symposium on computer architecture. pp. 234- 243 ,(1987) , 10.1145/30350.30377
Lamport, How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs IEEE Transactions on Computers. ,vol. 28, pp. 690- 691 ,(1979) , 10.1109/TC.1979.1675439
Philip Bitar, The weakest memory-access order Journal of Parallel and Distributed Computing. ,vol. 15, pp. 305- 331 ,(1992) , 10.1016/0743-7315(92)90047-Q
Kourosh Gharachorloo, Anoop Gupta, John Hennessy, Performance evaluation of memory consistency models for shared-memory multiprocessors Proceedings of the fourth international conference on Architectural support for programming languages and operating systems - ASPLOS-IV. ,vol. 19, pp. 245- 257 ,(1991) , 10.1145/106972.106997