PCI bus to IEEE 1394 bus translator employing pipe-lined read prefetching

摘要: A PCI bus to IEEE 1394 translator for coupling a device host computer via an bus. The translates addresses of cycles initiated by the into memory and performs data transfers between exchanging request response packets with using translated address. also received from cycle initiating targeted at addresses. posts sequential write write-posting FIFO until granted ownership combines single packet transmits on computer. translator, if configured first mode, pipelines subsequent posting once reception has been acknowledged but prior responding status indicating completion transaction, in particular whether or not resource conflict occurred. In read device, pre-fetches larger amount than specified pre-fetch order satisfy which are address sequence previous cycle. more becomes predetermined empty pipeline consumption transmission translator.