Hardware implementation of fair queuing algorithms for asynchronous transfer mode networks

摘要: Providing quality-of-service guarantees in both cell- and packet-based networks requires the use of a scheduling algorithm switches network interfaces. These algorithms need to be implemented hardware high-speed switch. The authors present number approaches implement hardware. They begin by presenting general methodology for design timestamp-based fair queuing that provide same bounds on end-to-end delay fairness as those weighted queuing, yet have efficient implementations. Based this methodology, describe two specific algorithms, frame-based starting potential-based discuss illustrative implementations may used cell packet with variable-size packets. A combining traffic shaper class schedulers is also presented interface devices, such an ATM segmentation reassembly device.