EMI REDUCTION CIRCUIT

摘要: PROBLEM TO BE SOLVED: To provide an EMI reduction circuit capable of reducing the stage number cells configuring a FiFo memory for SSCG (Spread Spectrum Clock Generator).SOLUTION: In circuit, outputs reference pulse signal which becomes active state with cycle predetermined input clock cycle, every modulation output clock. A is configured stages less than two times corresponding to maximum cumulative delay difference. When pointer anomaly detection part detects occurrence in pointer, generates state. holding holds period time until outputted by state, and as signal. reset resetting write generation read when both become states.