作者: James M Clark
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摘要: Frame synchronization for a binary data signal having multiframe including N frames, each of the frames M channels and first sync signal, at least one channel signals in different (N-1) subchannel second is accomplished by employing two detectors, being responsive to predetermined local timing therefor provide control indicative phase relation between these other signals. The are samples sampling circuits. outputs circuits applied decision whose cascade connected digital counters generators used generate necessary counter generator driven bit rate clock which inhibited when circuit associated therewith indicates an out-of-sync condition. frame from In embodiment, dual integrators generating separately inhibiting required. another single producing required, with cooperating manner clock.