Single slope A/D converter with sample and hold

摘要: A converter circuit employs a capacitor coupled through selector switch to an analog voltage so that the is charged level. When conversion commanded, disconnected from and discharged constant current load. This results in linear ramp. comparator senses compares it reference level slightly above ground. Upon starting ramp increment of larger than applied series with capacitor. drops below output used terminate interval. Thus, interval directly linearly proportional magnitude voltage. If desired, can be operate counter provide conventional digital readout. Alternatively, device operated by microprocessor readout being sensed displayed if desired microprocessor. Due voltage, zero fixed finite time.