Clock distribution circuit with active de-skewing

摘要: A clock distribution circuit with multiple drivers distributing a signal on paths has active de-skewing logic circuitry for equalizing the total delay to different recipient circuits in system. The uses return path parallel outward sense propagation and includes phase comparator inputs receiving reference comparison of their phase. Voltage-controlled elements, responsive control voltage provided by charge pump controlled comparator, adds or removes equal amounts until matches that signal. Each driver may have its own share common In one embodiment each time-shares pump, using sample-and-hold store voltages obtained comparisons. Input receivers selectable input buffers take into account buffer delays family types recipients.