Built-In Self-Test and Defect Tolerance for Molecular Electronics-Based NanoFabrics

作者: Mohammad Tehranipoor

DOI: 10.1007/978-90-481-8540-5_5

关键词:

摘要: In this chapter, a built-in self-test procedure is presented for testing and fault tolerance of molecular electronics-based nanoFabrics. The nanoFabrics are assumed to include up 1012 devices/cm2 as high 10% defect density; requires new test strategies that can efficiently diagnose the in reasonable time. BIST shown utilizes nanoFabric’s components small groups containing pattern generator response analyzer. Using will result higher diagnosability recovery. technique applies tests parallel with low number configurations resulting manageable time such large devices. Due density nanoFabrics, an efficient diagnosis must be done after achieve called recovery increase procedure. It increases available fault-free detected nano-chip. Finally, database map created used by compilers during configuring avoid defective components. This results reliable system constructed using unreliable

参考文章(30)
S.C. Goldstein, D. Rosewater, Digital logic using molecular electronics international solid-state circuits conference. ,vol. 1, pp. 204- 459 ,(2002) , 10.1109/ISSCC.2002.993007
J.G. Brown, R.D. Blanton, CAEN-BIST: testing the nanofabric international test conference. pp. 462- 471 ,(2004) , 10.1109/TEST.2004.1386982
Seth C. Goldstein, Mahim Mishra, Scalable Defect Tolerance for Molecular Electronics ,(2002)
C. Stroud, J. Nall, M. Lashinsky, M. Abramovici, BIST-based diagnosis of FPGA interconnect international test conference. pp. 618- 627 ,(2002) , 10.1109/TEST.2002.1041813
C. Stroud, E. Lee, M. Abramovici, BIST-based diagnostics of FPGA logic blocks international test conference. pp. 539- 547 ,(1997) , 10.1109/TEST.1997.639662
R. Rajsuman, Design and test of large embedded memories: An overview IEEE Design & Test of Computers. ,vol. 18, pp. 16- 27 ,(2001) , 10.1109/54.922800
James R Heath, Philip J Kuekes, Gregory S Snider, R Stanley Williams, A Defect-Tolerant Computer Architecture: Opportunities for Nanotechnology Science. ,vol. 280, pp. 1716- 1721 ,(1998) , 10.1126/SCIENCE.280.5370.1716
Mohammad Tehranipoor, Reza M. Rad, Fine-grained island style architecture for molecular electronic devices field programmable gate arrays. pp. 226- 226 ,(2006) , 10.1145/1117201.1117241
CP Collier, EW Wong, M Belohradský, FM Raymo, JF Stoddart, PJ Kuekes, RS Williams, JR Heath, Electronically Configurable Molecular-Based Logic Gates Science. ,vol. 285, pp. 391- 394 ,(1999) , 10.1126/SCIENCE.285.5426.391
R.M.P. Rad, M. Tehranipoor, SCT: an approach for testing and configuring nanoscale devices vlsi test symposium. pp. 370- 377 ,(2006) , 10.1109/VTS.2006.61