Data packet resequencer for a high speed data switch

摘要: A resequencing buffer (44) and a control circuit (46) is disclosed for data packets into their timed sequence after traversing switch fabric (22) which can introduce misordering of because the varying time intervals required to traverse in non-blocking manner. The controller includes plurality bi-directional shift registers (60) storing each packet's age slot number, register having an associated (62) feeding number one bit at onto contention bus (64) thereby determine oldest packet eligible transmission. exclusive OR wire interconnects circuits output (68) controls containing age. In event ties between same age, numbers are used select