Automatic bus macro placement for partially reconfigurable FPGA designs

摘要: Dynamic Partial Reconfiguration of FPGAs partitions the configurable logic fabric into static and reconfigurable regions. The regions' functionality changes at run time while regions continue unperturbed. interface via fixed connection points ("bus macros"). We introduce notion a fitness score as measure how well combined designs meet their timing constraints, subject to given bus macro placement. present tool that uses design-space exploration obtain automatic, near-optimal placements. achieves 76% better scores over manual location macros around region has noticeable impact on timings, we found this is accurately reflected our score. also following accepted best design practices leads quantifiably sub-optimal placements, underscoring need for such tool.