Sense amplifier circuit for detecting degradation of digit lines and method thereof
作者： Roland Ochoa , Daniel R. Loughmiller
DOI:
关键词:
摘要: To permit effective testing of a sense amplifier circuit, the is designed to be responsive data stored in selected memory cell controlled test mode. The circuit includes pull-down having delay receive and respond control signal which indicates whether sensing operate mode or normal also an output configured arranged generate reference corresponding cell. sufficient time for correct values at signal, delayed response indicating that
google.nl 参考文章(13)
Loren L. McLaury, Integrated circuit memory with isolation of column line portions through P-sense amplification period ,(1992)
Donald M. Morgan, Simplified low power flash write operation ,(1991)
Stephen L. Casper, Sense amplifier pulldown circuit for minimizing ground noise at high power supply voltages ,(1992)
Loren L. McLaury, Memory with isolated digit lines ,(1993)
Ward D. Parkinson, Stephen L. Casper, Sense amplifier pulldown device with tailored edge input ,(1989)
Loren L. McLaury, Integrated circuit memory with dual P-sense amplifiers associated with each column line ,(1992)
Wen-Foo Chern, Method for providing multi-level potentials at a sense node ,(1992)
Paul S. Zagar, Michael W. Starkweather, Method and apparatus for providing a faster ones voltage level restore operation in a dram ,(1992)
Loren L. McLaury, DRAM with a two stage voltage pull-down sense amplifier ,(1992)