作者: Joseph M. Moran , David B. Fraser , Dan Maydan
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摘要: In an integrated circuit fabrication sequence, a relatively thick sacrificial layer (18) is deposited on nonplanar surface of device wafer in which high-resolution features are to be defined. The characterized by conforming lower and essentially planar top the capability being patterned way. An intermediate masking (22) then thin resist (20) layer, thickness insufficient itself provide adequate step coverage if were applied directly surface. A pattern defined transferred into layer. Subsequently, dry processing technique utilized replicate with near-vertical sidewalls thereby produced By means underlying