Processor performing packed data multiplication
作者： Larry M. Mennemeier , Alexander Peleg , Benny Eitan , Yaakov Yaari , Millind Mittal
DOI:
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摘要: A processor. The processor includes a decoder being coupled to receive control signal. signal has first source address, second destination and an operation field. address corresponds location. third field indicates that type of packed data multiply is be performed. further circuit the decoder. for multiplying stored at location with communicating corresponding result
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