Time-to-Digital Conversion for Digital Frequency Synthesizers
作者： Michael H. Perrott
DOI: 10.1016/B978-0-12-398326-8.00012-1
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摘要: Time-to-digital converter (TDC) circuits are a key component for achieving high-performance digital phase-locked loops (PLLs) which offer lower area and greater flexibility than their analog PLL counterparts. This chapter focuses on recently developed TDC architecture known as the gated ring oscillator (GRO) offers first-order shaping of its quantization noise delay stage mismatch. To provide context GRO discussion, background general implementation techniques is described along with performance issues related to frequency synthesizers. The concept then presented, followed by details measured results. Finally, recent variations such MASH structure achieves higher-order switched (SRO) improves robustness dead zones encountered TDC.
sci-hub.se 参考文章(16)
R.T. Baird, T.S. Fiez, Linearity enhancement of multibit /spl Delta//spl Sigma/ A/D and D/A converters using data weighted averaging IEEE Transactions on Circuits and Systems Ii: Analog and Digital Signal Processing. ,vol. 42, pp. 753- 762 ,(1995) , 10.1109/82.476173
Matthew A. Z. Straayer, Noise shaping techniques for analog and time to digital converters using voltage controlled oscillators Massachusetts Institute of Technology. ,(2008)
Gabor C. Temes, Steven R. Norsworthy, Richard Schreier, Ieee Circuits, Delta-sigma data converters : theory, design, and simulation IEEE Press. ,(1997)
A.M. Abas, A. Bystrov, D.J. Kinniment, O.V. Maevsky, G. Russell, A.V. Yakovlev, Time difference amplifier Electronics Letters. ,vol. 38, pp. 1437- 1438 ,(2002) , 10.1049/EL:20020961
Sang-Hye Chung, Kyu-Dong Hwang, Won-Young Lee, Lee-Sup Kim, A high resolution metastability-independent two-step gated ring oscillator TDC with enhanced noise shaping international symposium on circuits and systems. pp. 1300- 1303 ,(2010) , 10.1109/ISCAS.2010.5537261
Amr Elshazly, Sachin Rao, Brian Young, Pavan Kumar Hanumolu, A 13b 315fs rms 2mW 500MS/s 1MHz bandwidth highly digital time-to-digital converter using switched ring oscillators international solid-state circuits conference. pp. 464- 466 ,(2012) , 10.1109/ISSCC.2012.6177092
Matthew Z. Straayer, Michael H. Perrott, A Multi-Path Gated Ring Oscillator TDC With First-Order Noise Shaping IEEE Journal of Solid-state Circuits. ,vol. 44, pp. 1089- 1098 ,(2009) , 10.1109/JSSC.2009.2014709
Seog-Jun Lee, Beomsup Kim, Kwyro Lee, A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme IEEE Journal of Solid-state Circuits. ,vol. 32, pp. 289- 291 ,(1997) , 10.1109/4.551926
Stephan Henzler, Siegmar Koeppe, Dominik Lorenz, Winfried Kamp, Ronald Kuenemund, Doris Schmitt-Landsiedel, A Local Passive Time Interpolation Concept for Variation-Tolerant High-Resolution Time-to-Digital Conversion IEEE Journal of Solid-state Circuits. ,vol. 43, pp. 1666- 1676 ,(2008) , 10.1109/JSSC.2008.922712
T.E. Rahkonen, J.T. Kostamovaara, The use of stabilized CMOS delay lines for the digitization of short time intervals IEEE Journal of Solid-state Circuits. ,vol. 28, pp. 887- 894 ,(1993) , 10.1109/4.231325