Hardware Architecture for CSMA/CA Algorithm for IEEE 802.15.4 LR-WPANs

作者: Nandamuri Raja , Shashank Gavel , Ajay Singh Raghuvanshi

DOI: 10.1109/IEMECONX.2019.8877018

关键词:

摘要: The rapid growth in the latest IoT and wireless technologies are demanding low power, high reliability, latency applications. makes use of IEEE Std 802.15.42015 which supports In this paper, combined hardware architecture for both slotted unslotted CSMA/CA channel accessing algorithm has been proposed. We have proposed a new design that is efficient as compared to earlier existing hardware. performance analyzed XC3S700AN device various input message bit sizes by using Verilog HDL. maximum clock frequency increased 87% best available 2-bit input.

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