作者: Jae Dong Chung , Massoud Kaviany
DOI: 10.1016/S0017-9310(99)00165-9
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摘要: Abstract The observed low effective thermal conductivity of porous silicon makes for its convenient fabrication and integration as a insulation layer in microelectronics. average pore size is controlled by the etching process ranges between 1 100 nm, which on end much less than bulk phonon mean-free path. This conductivity, i.e., path, can be explained with inclusion effects scattering randomness. available two-dimensional pore-network simulations are used along Boltzmann transport equation to determine conductivity. It shown that hindering effect (due reflection from solid-pore interface) significant small size. Also, due dendritic structure pores, randomness significant. predictions compared existing experiments good agreement found.