摘要: Growing interest in ambitious multiple-issue machines and heavilypipelined requires a careful examination of how much instructionlevel parallelism exists typical programs. Such an is complicated by the wide variety hardware software techniques for increasing that can be exploited, including branch prediction, register renaming, alias analysis. By performing simulations based on instruction traces, we model at limits feasibility even beyond. This paper presents results 18 different test programs under 375 models available replaces Technical Note TN-15, earlier version same material.
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