An Analysis of Microarchitecture Vulnerability to Soft Errors on Simultaneous Multithreaded Architectures

摘要: Semiconductor transient faults (i.e. soft errors) have become an increasingly important threat to microprocessor reliability. Simultaneous multithreaded (SMT) architectures exploit thread-level parallelism improve overall processor throughput. A great amount of research has been conducted in the past investigate performance and power issues SMT architectures. Nevertheless, effect execution on a microarchitecture's vulnerability error remains largely unexplored. To address this issue, we developed microarchitecture level analysis framework for Using mixed set SPEC CPU 2000 benchmarks, quantify impact multithreading wide range structures. We examine how baseline reliability profile varies with workload behavior, number threads fetch policies. Our experimental results show that rises architectures, while each individual thread shows less vulnerability. By considering both reliability, outperforms superscalar The its tradeoff vary across different With detailed results, point out potential opportunities reduce vulnerability, which can serve as guidance exploiting thread-aware optimization techniques near future. our knowledge, paper presents first effort characterize processors