A bandwidth tracking technique for a 65nm CMOS digital phase-locked loop
作者： Jay Maxey , Chih-Kong Ken Yang , Ping-Hsuan Hsieh
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摘要: This paper presents a technique to achieve the bandwidthtracking ability of digital PLLs used for clock generation in large systems. The uses replica delay cells DCO and PD ≫100× range operating frequency. Measurement results show near constant damping factor tracking loop bandwidth reference frequency over 2× core oscillation frequencies (2.5GHz–5.0GHz) from 19.5MHz 312MHz without calibration.
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